Binarizing a polynomial Kolmogorov--Arnold Network (KAN) not only changes parameter precision, but also alters the function space available to each layer. When activations are restricted to ${-1,+1}$, all even powers reduce to $1$ and all odd powers reduce to $x$, causing the elementwise polynomial basis to collapse to constant and first-order responses. We refer to this structural failure as Spatial Orthogonality Collapse. Our proposed BiKAN addresses this critical issue by augmenting each binary KAN layer with selected degree-2 Walsh characters. Fixed circular channel rolls generate pairwise parities, and learned binary projections mix them using the same XNOR--popcount operations as the remaining W1A1 paths. This restores explicit pairwise coordinates without learned routing or multiplier-based feature generation. Experiments on CIFAR-10 confirms that removing parity reduces accuracy by $1.23$ points over five paired seeds ($p=0.003$), the gain increases as width decreases, and accuracy improves monotonically as more parity planes are added. At an equal $\sim$11.9M-parameter budget, parity outperforms conventional widening by $3.09$ points ($p<10^{-4}$). At W1A1, BiKAN reaches $99.48\%$, $84.38\%$, and $55.81\%$ on MNIST, CIFAR-10, and CIFAR-100, respectively. Post-route Zynq-7020 FPGA results show that the repair remains hardware-efficient; the convolutional design cuts DSP usage from 164 to 72 and estimated compute-core latency from 401 to 54.8 ms, while the power-of-two-aware dense design achieves zero-DSP inference with a 0.03-point accuracy loss. The BiKAN implementation is available at https://github.com/OSU-STARLAB/BiKAN.
Learned feature reweighting can improve automatic modulation classification (AMC) in software, but the same operation introduces additional arithmetic and latency when implemented on an FPGA. This work measures that trade-off in a compact fixed-point classifier using 24 sparse DFT-energy features, 8 phase/statistical features, and a 32-to-128-to-11 multilayer perceptron. A second architecture inserts a learned 32-element, 8-bit, input-dependent gate before the classifier. Gated and ungated models are trained using post-training quantization (PTQ) and quantization-aware training (QAT) with two matched training seeds. The resulting eight checkpoints are compiled independently for an Intel Cyclone V FPGA and evaluated over 352,000 physical-board classifications. Ungated models achieve higher test accuracy in all four matched gate comparisons, with mean gated-minus-ungated differences of -0.784 percentage points under PTQ and -0.616 percentage points under QAT. The effect of QAT changes direction between the two training seeds. In hardware, the gate adds an average of 1,318 adaptive logic modules (ALMs), 1,557 registers, 4 DSP blocks, and 3,140 processing cycles. All 352,000 board predictions agree exactly with an independent integer reference, and 3,760 captured intermediate values from one training seed also match. For this feature representation and implementation, learned gating increases FPGA cost without improving classification accuracy.