Runtime thermal management of high-performance chips depends on fast and accurate full-chip thermal maps. Conventional simulators typically estimate power traces from performance metrics first, which adds overhead. This work proposes TherMapNet, an attention-guided thermal simulator that predicts full-chip thermal maps directly from performance metrics. A Transformer encoder captures temporal evolution by treating the time series of each metric as a token, improving modeling of dynamic workloads. A CNN then extracts fine-grained spatial features. For the CNN, a dual-branch channel-spatial attention convolution module (DACM) and a triplet loss are used to improve spatial learning and reconstruction accuracy. TherMapNet is applied to a multi-core CPU (AMD Ryzen 7 4800U) and a many-core GPU (NVIDIA GeForce RTX 4060). Experiments show that it outperforms prior thermal simulators, with RMSE below 0.26 C and inference under 2.4 ms on an NVIDIA GeForce RTX 3090 GPU. These results indicate that TherMapNet can support high-quality runtime thermal management of modern multi-core chips.
Recent developments in large language models (LLMs) and tool-using agents encourage people to explore the potential of using agents in chip design. The core question is what kind of AI we really need in such a sophisticated industry. To this end, we bring the idea of modeling a chip-design superintelligence as an enormous \textit{AI-organization}.
Phat Tieu, Sayanti Jana, Matthew DeLorenzo +5cs.AR cs.AI cs.MA cs.SE
Modern chip design relies on electronic design automation (EDA) tools that generate large, heterogeneous artifacts, including source files, scripts, logs, netlists, and reports. Analyzing these artifacts is critical for debugging, optimization, and design-flow understanding, but remains difficult because relevant evidence is often distributed across many artifact types and design stages. Although LLM agents show promise for EDA assistance, existing approaches lack public benchmarks for large-scale cross-artifact analysis and often struggle to ground reasoning in tool-generated evidence. We present EDATracer, an agentic framework for evidence-grounded EDA artifact analysis. EDATracer organizes design artifacts into a knowledge graph paired with a semantic vector index, enabling LLM agents to retrieve evidence across source files, logs, netlists, and reports. We curate an 18.9 GB dataset of 2,787 synthesizable open-source chip designs and introduce a 90-question benchmark spanning factual, statistical, and reasoning tasks. Across evaluated agents, EDATracer achieves the best pass@1 accuracy, outperforming Cursor and Claude Code by 6.4 and 7.2 percentage points on average, while using 2.0-3.2x fewer tokens.
Macro placement is a fundamental step in modern chip physical design, playing a crucial role in determining the solution quality of high-dimensional combinatorial optimization problems. Despite recent advancements in machine learning for spatial coordinate determination, the temporal dimension of placement sequencing remains largely governed by static heuristics. In this work, we demonstrate that the placement sequence is not merely a preprocessing step but a decisive factor in optimization, where suboptimal early decisions trigger irreversible domino effects that constrain the solution space. To harness this unexplored dimension, we propose \textbf{OrderPlace}, a proxy-guided LLM evolution framework for automatically discovering macro placement order strategies. Instead of relying on manually crafted heuristics such as area- or connectivity-based ordering, OrderPlace explores a broader space of code-level policies, ranging from static scoring metrics to dynamic physics-inspired mechanisms. To mitigate the prohibitive cost of evaluating sequences, we introduce a lightweight proxy evaluation mechanism that efficiently filters candidates using a deterministic greedy probe. Experimental results on the standard ISPD 2005 benchmarks demonstrate that OrderPlace discovers novel ordering strategies. Compared with WireMask-EA and the state-of-the-art method EGPlace, OrderPlace reduces wirelength by 34.04\% and 14.08\%, respectively.