A graph layout is normally a table of $N$ free coordinates. We optimise a function with a fixed number of parameters instead. This gives a drawing a sample complexity and an extensible domain. Force-directed algorithms remain the standard tools for graph drawing. The most accurate among them minimise stress in the Kamada-Kawai formulation by directly optimising the node coordinates, at a full objective cost of $O(N^2)$ in time and space. Here, we propose Fling (Field Layout via Implicit Neural Geometry), a small neural network mapping the distances of each node to a set of landmarks, positioning it in the plane by training on the layout energy. The full spring system then becomes tractable without its distance matrix, as rest lengths follow from a landmark bound in constant time per pair while a second network learns the majorisation sums from exact anchor rows, at $O(|\mathcal{A}|N)$ per step for $|\mathcal{A}|\ll N$ anchors. Unlike neural drawers that read the graph by message passing, we represent the drawing as a function of node features. An unseen node costs one forward pass, where sparse and low-rank majorisation remain transductive. As the unknowns are weights rather than coordinates, the energy only requires a small fraction of the nodes, and a field fitted that way outperforms PivotMDS, landmark MDS, and a kernel ridge trained on the same energy and features, when the task is fitting the energy of a graph from a sample of its nodes. In addition, the same parameterisation enables a stochastic pivot stress variant, an aesthetics-optimised variant carrying a neighbour-embedding energy with node-edge clearance and crossing terms on the same field, and conditioning on the weight between two energies gives a whole layout family from one run.
Converting a SPICE netlist into a human-readable schematic is a longstanding problem in electronic design automation: simulators and machine-learning pipelines readily produce netlists, but designers reason about circuits through diagrams. Recent learning-based approaches translate netlists into schematics probabilistically, yet they provide no guarantee that the generated drawing preserves the original connectivity, and their accuracy degrades sharply as circuits grow. We present Weave, a deterministic converter that turns a SPICE netlist into an LTspice .asc schematic using a layered (Sugiyama-style) graph layout, and that certifies every output by a round-trip connectivity check: the generated schematic is re-parsed into a netlist and compared, net for net, against the input. A result is reported as correct only when the two partitions are identical, giving a binary correctness certificate rather than a similarity score. Weave runs entirely client-side as a single dependency-free file and embeds a pin table for 5093 LTspice symbols. On the identical public Circuits-LTSpice test set used by the state-of-the-art LLM converter Schemato (117 circuits, netlisted with LTspice itself), Weave achieves 100% compilation and 100% round-trip-verified connectivity equivalence, compared with Schemato's reported 76% compilation and a graph-edit-distance similarity of 0.35; notably, 73% of that set exceeds the five-component threshold beyond which Schemato reports losing connectivity accuracy. On a larger and harder corpus, the 3460 netlistable circuits of the official Analog Devices LTspice demo collection, Weave verifies exact connectivity for 88.4% of circuits, with the remaining failures concentrated in a single, well-characterized class of dense multi-pin power modules.